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Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
FEATURES
* 9 single ended LVCMOS/LVTTL outputs; (8) clocks, (1) feedback * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL * Maximum output frequency: PLL Mode, 175MHz * VCO range: 250MHz to 700MHz * Output skew: 75ps (maximum) * Cycle-to-cycle jitter: 50ps (maximum) * Static phase offset: 90ps 110ps * 3.3V supply voltage
GENERAL DESCRIPTION
The ICS86953I-147 is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Clock HiPerClockSTM Generator and a member of the HiPerClock TM S family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pair can accept most standard differential input levels. With output frequencies up to 175MHz, the ICS86953I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS86953I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
ICS
PIN ASSIGNMENT
VCO_SEL nBYPASS PLL_SEL GND GND VDDO QFB Q0
* -40C to 85C ambient operating temperature * Pin compatible to the MPC953
32 31 30 29 28 27 26 25 VDDA FB_CLK nc nc nc nc GND PCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
nPCLK MR/nOE VDDO Q7 GND Q6 VDDO Q5
24 23 22
Q1 VDDO Q2 GND Q3 VDDO Q4 GND
ICS86953I-147
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
BLOCK DIAGRAM
PCLK nPCLK FB_CLK VCO_SEL nBYPASS MR/nOE PLL_SEL 0 Phase Detector 0 LPF VCO 1 /2 1 /4 0 1 7
QFB
/
Q0:Q6
Q7
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Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
Type Power Input Unused Power Input Pullup Pullup Description Analog supply pin. Feedback clock input. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Non-inver ting LVPECL differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4, 5, 6 7, 13, 17, 21, 25, 29 8 Nam e VDDA FB_CLK nc GND PCLK
Pullup/ Inver ting LVPECL differential clock input. 9 nPCLK Input Pulldown Internally biased to VDDO/2. Active HIGH Master Reset. Active LOW output enable. When logic High, the internal dividers are reset and the outputs are 10 MR/nOE Input Pulldown tri-stated (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Power Output supply pins. 11, 15, 19, 23, 27 VDDO 12, 14, 16, 18, Q7, Q6, Q5, Q4, Clock outputs. LVCMOS / LVTTL interface levels. Output 20, 22, 24, 26 Q3, Q2, Q1, Q0 14 typical output impedance. Feedback clock output. LVCMOS / LVTTL interface levels. 28 QFB Output 14 typical output impedance. Selects VCO when HIGH. When LOW, selects PCLK, 30 PLL_SEL Input Pullup nPCLK. LVCMOS / LVTTL interface levels. 31 nBYPASS Input Pullup Selects PLL when HIGH. When LOW, in Bypass mode. Selects VCO /2 when HIGH. Selects VCO /1 when LOW. 32 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CP D ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDDA, VDDO = 3.465V 5 Test Conditions Minimum Typical 4 51 51 7 14 12 Maximum Units pF K K pF
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Input MR/nOE 1 0 Outputs QFB, Q0:Q7 HiZ Enabled
TABLE 3B. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs Bypass 0 1 1 1 1
86953BYI-147
PLL_SEL X 0 0 1 1
VCO_SEL X 0 1 0 1
Operation Test Mode: PLL and divider bypass Test Mode: PLL bypass Test Mode: PLL bypass PLL Mode PLL Mode
Outputs QFB, Q0:Q7 CL K CLK/4 CLK/8 VCO/4 VCO/8
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Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDDA VDDO IDDA IDDO Parameter Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 20 75 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VIH Parameter Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 IOH = -20mA IOL = 20mA VDD - 0.6 0.6 VCO_SEL, nBYPASS, PLL_SEL, MR/nOE FB_CLK VCO_SEL, nBYPASS, PLL_SEL, MR/nOE FB_CLK Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 120 Units V V V V A V V
VIL IIN VOH VOL
NOTE: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load Test Circuit".
TABLE 4C. LVPECL DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol IIN V PP Parameter Input Current Peak-to-Peak Input Voltage 0.15 Test Conditions Minimum Typical Maximum 120 1.3 VDD - 0.85 Units A V V
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
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ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
Test Conditions Minimum Typical Maximum 175 Units MHz
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fREF Parameter Input Reference Frequency
TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter PLL Mode Output Frequency Propagation Delay; NOTE 1 PLL Mode Bypass Mode PCLK, nPCLK Measured on rising edge at VDD/2 -20 20% to 80% 100 47 50 90 2.5 Test Conditions VCO_SEL = 1 VCO_SEL = 0 Minimum 31.25 62.50 Typical Maximum 87.5 175 200 4 75 50 200 700 53 10 6 Units MHz MHz MHz ns ps ps ps ps % ms ns ns
tsk(o) tjitter(cc)
t(O) tR / tF odc tLOCK t EN
Output Skew; NOTE 2, 4 Cycle-to-Cycle Jitter; NOTE 5 Static Phase Offset; NOTE 3, 5 Output Rise/Fall Time Output Duty Cycle PLL Lock Time Output Enable Time; NOTE 4
Output Disable Time; NOTE 4 7 tDIS NOTE: Termination of 50 to VDD/2. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% V DD
VDDA, VDDO
SCOPE
nPCLK
Qx
V
PP
LVCMOS
GND
Cross Points
V
CMR
PCLK
GND -1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
V V V
DIFFERENTIAL INPUT LEVEL
V
DDO
DDO
DDO
Q0:Q7, QFB
Clock Outputs 20%
2
2
2
DDO
Qx
2
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
80%
tR
OUTPUT RISE/FALL TIME
V
Q0:Q7 QFB
Pulse Width t
PERIOD
odc =
t PW t PERIOD
t(O)
tjit(O) = t(O) -- t(O) mean = Phase Jitter
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PHASE JITTER & STATIC PHASE OFFSET
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DDO
tcycle n+1
V
DDO
Qy
2 tsk(o)
OUTPUT SKEW
nPCLK
80%
PCLK
20% tF
Q0:Q7, QFB
VDDO 2 t
PD
PROPAGATION DELAY
nPCLK
2
VOH VOL VOH VDDO
PCLK
FB_CLK
VOL
2
Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS86953I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDDO .01F VDDA .01F 10 F 10
FIGURE 2. POWER SUPPLY FILTERING
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REV. B APRIL 23, 2004
Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
PCLK/nPCLK CLOCK INPUT INTERFACE
The PCLK/ nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3 125
R4 125
PCLK
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
C1
R3 1K
R4 1K
PCLK
C2
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
Zo = 50 Ohm
nPCLK
HiPerClockS PC L K /n PC LK
R1 1K
R2 1K
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS86953I-147 layout example is shown in Figure 4A. The ICS86953I-147 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will
VDD
R10 1K
R8 1K
R9 1K
R1
36
Zo = 50
VDD
R7 10 - 15
U1
VCO_SEL nBYPASS PLL_SEL GND QFB VDDO Q0 GND
32 31 30 29 28 27 26 25
C16 10u
C11 0.01u
VCC
Zo = 50 Ohm
Zo = 50 Ohm
VDD
LVPECL Driv er
9 10 11 12 13 14 15 16
ICS86953I-147
nPCLK MR/nOE VDDO Q7 GND Q6 VDDO Q5
1 2 3 4 5 6 7 8
VDDA FB_CLK nc nc nc nc GND PCLK
Q1 VDDO Q2 GND Q3 VDDO Q4 GND
24 23 22 21 20 19 18 17
Zo = 50
R3 50
R4 50
R6 1K
R2
36
C6 (Option) 0.1u
R5 50
(U1-11)
VDD
(U1-15)
(U1-19)
(U1-23)
(U1-27)
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF
C1 0.1uF
FIGURE 4A. ICS86953I-147 LVCMOS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The series termination resistors should be located as close to the driver pins as possible.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
50 Ohm Trace
C1
GND
R1
VDD
VIA
Other signals
C5
R7
C16
VCCA
U1
Pin 1
C11
C4
R2
C2
C3
50 Ohm Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS86953I-147
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Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86953I-147 is: 1758
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ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
Marking ICS6953BI147 ICS6953BI147 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS86953BYI-147 ICS86953BYIT-147
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 86953BYI-147
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REV. B APRIL 23, 2004
Integrated Circuit Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
REVISION HISTORY SHEET Description of Change Added Pullup/Pulldown to Pin 9. Pin Characteristics table - changed CIN limit from 4pF max. to 4pF typical. Added 5pF min. and 7pF typical to CPD. Updated Figure 3C and 3D. Added Layout Guideline and PCB Board layout. Pin Characteristics Table - added ROUT row. Date
Rev
Table T1 T2
Page 2 2 7 8&9 2
B
10/28/03
B
T2
4/23/04
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